Applications

Pixer Enables Technology For:

Mask Makers

  • Tune your masks to meet required CD specifications and for optimal performance
  • Yield improvement and fast turn-around on all mask types
  • Achieve advanced CD Uniformity & MTT specifications
  • Leverage existing installed mask manufacturing equipment
  • Postpone purchasing additional advanced writing and etching tools

IC Manufacturers

  • Improve your Lithography Process Window (PW) and overall productivity
  • "Pellicle on" CD Uniformity improvement
  • Extend the life of your installed base of scanners by improving the PW
  • Improve yield on specific critical mask levels: dry and immersion lithography
  • Improve chip binning: higher speed, lower leakage, etc.

Currently available applications on the Pixer CDC200.  These applications are being used in production at multiple customer sites on production masks:

  • Improvement of Global CD uniformity induced by photomasks
  • Improvement of Global CD uniformity induced by the litho process
  • Local Critical Dimension control (in a die)

Mask Applications

The input measurements are taken from the reticle surface either by a CD-SEM for reticle, Optical CD or AIMS™ . The mask CD variation map reflects the mask manufacturing process, where the main contributors are the blank itself and process-related systematic and random errors such as write tool proximity effects, and developer and etch signatures.  After correction of the mask with the CDC200 to eliminate these CD variations, the improvement can be observed and verified either by AIMS or by printing the reticle on a wafer.

Example of Mask Application with the Pixer CDC200

Eliminating Mask Induced CD Uniformity Error


Wafer/Lithography Applications

The input measurements are taken from the wafer surface either by a CD-SEM or OCD (scatterometry). The CD variation map of the wafer field reflects the entire litho process, where the main contributors are the mask itself, the illumination non-uniformity, the stepper/scanner optics in general and the lens aberration in particular, the scanner slit active area, the resist, etc.
If post-etch measurements are used as an input, it is possible to include etch effects in the correction as well.
After the CDC200 corrects the mask through the pellicle and eliminates the CD variations, the mask is reprinted on the wafer using the same exact lithography process, to observe the CD uniformity (CDU) improvement.
Example of Wafer/Lithography Application with the Pixer CDC200:

Eliminating Litho Induced CD Uniformity Error


System on a Chip (SoC) and Shuttle Mask Applications

These applications are well-known for their challenging CD control requirements. This results from combining different device types with different pattern densities and pitches in the same chip.  This combination often results in local CD “hot spots” that make reaching CD uniformity targets very difficult.

CDC200 is ideally positioned to eliminate any local CD bias, thereby expanding the lithography process window (PW) and therefore improve EOL yield.  CDC200 can easily compensate for local hotspots or pattern density variations that are reflected in the CD map.

Eliminating Design Related CD Error


Multiple CD Control (M-CDC) Application

M-CDC is an advanced application of the CDC200.  M-CDC offers the ability to fine-tune the results achieved in the 1st correction if needed. M-CDC works by applying an additional correction layer 100µm above the original correction layer.

The M-CDC is useful to:

  • Adjusting mask signature only CDC-corrected masks to include wafer process CD uniformity errors further improving CD uniformity
  • Fine tuning previously CDC-corrected masks to achieve additional improvements in CD uniformity
  • Error correction
  • Apply CDC process to adjust for litho process changes

Mask Cross Section
M-CDC Example (DRAM Actual Chip)

Larger than X2 CDU Improvements Using M-CDC Application

  • Mask & Litho induced - CD Uniformity improvement
  • Local CD Control
  • All type of masks (Bin, AEPSM, AAPSM, CPL)
  • No feature size limitation
  • Memory, Flash and Logic devices
  • System-on-Chip (SOC)
  • Shuttle masks
  • M-CDC (Multiple CDC)